Memory devices are digital circuits and operate on clock signals in order for different parts thereof to act on a synchronized schedule. However, a clock signal received by a memory device may reach different parts thereof through different paths and at different times. Such mismatch between different signal paths results in problems, one of which being a reduced read margin of the memory device. FIGS. 1, 2, 3A, and 3B illustrate the problem of reduced read margin due to the different clock signal delays and a conventional technique for overcoming the problem.
FIG. 1 shows a portion of a memory device 100. Memory device 100 includes one or more memory arrays 102 (only one of which is shown). Each memory array 102 includes a plurality of memory cells 104 arranged in a plurality of rows and a plurality of columns, each row corresponding to a word line WL (WL0, WL1, . . . ) and each column corresponding to a pair of bit lines, BL and BL_ ((BL0, BL_0), (BL1, BL_1), (BL2, BL_2) . . . ). A word line decoder 106 receives word line address signals (“WL ADDR”) and provides word line signals to select one of word lines WL of memory array 102. A bit line decoder 108 receives bit line address signals (“BL ADDR”) and provides bit line signals Y (Y0, Y1, Y2, . . . ) to select a pair of bit lines BL and BL_of memory array 102 through switches 110. Each switch 110 may comprise a pair of NMOS transistors, and is turned on and off by bit line signals Y. Each memory cell 104 may be selected by selecting the corresponding word line and pair of bit lines. An I/O circuit 112 is coupled to bit lines BL and BL_to detect the datum stored in the selected memory cell 104 and to output the same. A control signal CTRL is provided to word line decoder 106 and I/O circuit 112 as a clock signal to trigger the operations thereof. For example, on an edge (rising edge or falling edge) of control signal CTRL, word line decoder 106 may decode the word line address and I/O circuit 112 may detect a datum stored in a selected memory cell 104 and output the same. Memory device 100 also includes a plurality of precharging PMOS transistors 114 each coupling a corresponding bit line BL or BL_ to a power supply voltage Vcc to precharge the corresponding bit line BL or BL_, thereby increasing a speed of accessing memory cells 104.
Memory cells 104 may comprise any suitable structure, such as a conventional 6-transistor structure shown in FIG. 2. FIG. 2 shows one memory cell 104 including two PMOS transistors 202 and 204 and four NMOS transistors 206, 208, 210, and 212. Each of MOS transistors 202, 204, 206, 208, 210, and 212 has a gate, a source, a drain, and a substrate. The gate of PMOS transistor 202, the gate of NMOS transistor 206, the drain of PMOS transistor 204, the drain of NMOS transistor 208, and the source of NMOS transistor 212 are all coupled to one another. The gate of PMOS transistor 204, the gate of NMOS transistor 208, the drain of PMOS transistor 202, the drain of NMOS transistor 206, and the source of NMOS transistor 210 are all coupled to one another. The sources and substrates of PMOS transistors 202 and 204 are coupled to power supply voltage Vcc. The sources and substrates of NMOS transistors 206 and 208 and the substrates of NMOS transistors 210 and 212 are grounded. The gates of NMOS transistors 210 and 212 are coupled to receive the word line signal WL. The drain of NMOS transistor 210 is coupled to bit line BL. The drain of NMOS transistor 212 is coupled to bit line BL_. Thus, PMOS transistor 202 and NMOS transistor 206 form an inverter 214, and PMOS transistor 204 and NMOS transistor 208 form an inverter 216. Inverters 214 and 216 are coupled to form a loop and may stably store a bit of datum. If the drains of PMOS transistor 202 and NMOS transistor 206 are at a logic high, i.e., approximately Vcc, then the drains of PMOS transistor 204 and NMOS transistor 208 are at a logic low, i.e., approximately ground, and memory cell 104 may be considered to have stored therein a logic high datum. If the drains of PMOS transistor 202 and NMOS transistor 206 are at logic low, then the drains of PMOS transistor 204 and NMOS transistor 208 are at logic high, and memory cell 104 is considered to have stored therein a logic low datum. When NMOS transistors 210 and 212 are turned on by word line signal WL, the datum stored in memory cell 104 and its reverse respectively appear on corresponding bit lines BL and BL_.
FIG. 2 also shows two of precharging PMOS transistors 114, 114-1 and 114-2, each having a gate, a drain, and a source. The gates of precharging PMOS transistors 114-1 and 114-2 are coupled to receive control signal CTRL. The sources of precharging PMOS transistors 114-1 and 114-2 are coupled to power supply voltage Vcc. The drain of precharging PMOS transistor 114-1 is coupled to bit line BL. The drain of precharging PMOS transistor 114-2 is coupled to bit line BL_. Switch 110 is shown to include NMOS transistors 218 and 220, each having a gate, a drain, and a source. The gates of NMOS transistors 218 and 220 are coupled to bit line decoder 108 to receive bit line signal Y. The drain of NMOS transistor 218 is coupled to bit line BL. The drain of NMOS transistor 220 is coupled to bit line BL_. I/O circuit 112 is coupled to the sources of NMOS transistors 218 and 220. Thus, when one memory cell 104 is selected, corresponding NMOS transistors 218 and 220 are turned on, corresponding NMOS transistors 210 and 212 are also turned on, corresponding PMOS transistors 114-1 and 114-2 are turned off, and I/O circuit 112 is allowed to access the datum stored in the selected memory cell 104 through corresponding bit lines BL and BL_. Then, on an edge of control signal CTRL, I/O circuit 112 is triggered to detect voltages on bit lines BL and BL_, amplifies a differential voltage across bit lines BL and BL_, and outputs the amplified differential voltage.
Due to parasitic resistances and capacitances, bit lines BL and BL_ corresponding to the selected memory cell 104 do not instantly exhibit the datum stored in the selected memory cell 104. Rather, if the datum stored in the selected memory cell 104 is a logic low, the corresponding bit line BL is gradually discharged from a precharged logic high state to a logic low state. Conversely, if the datum stored in the selected memory cell 104 is a logic high, the corresponding bit line BL_ is gradually discharged from a precharged logic high state to a logic low state. A read margin is defined as the differential voltage across the corresponding pair of bit lines BL and BL_ when I/O circuit 112 is triggered to detect the voltages on bit lines BL and BL_ Because I/O circuit 112 can only detect a differential voltage above a certain level, e.g., 100 mV, a small read margin, if below that certain level, may result in a read failure. To avoid a read failure, the triggering of I/O circuit 112 should be delayed to allow the differential voltage across bit lines BL and BL_ to develop and exceed the detectable level of I/O circuit 112, i.e., to ensure a read margin exceeding the detectable level of I/O circuit 112. A conventional technique for delaying the triggering of I/O circuit 112 is by using a tracking circuit, an example of which is shown in FIG. 3A.
In FIG. 3A, a tracking circuit 302 is shown to include a pair of dummy bit lines DBL and DBL_ and several tracking cells 304. A conventional tracking circuit, such as tracking circuit 302, may include five or more tracking cells 304. Tracking circuit 302 receives and delays control signal CTRL. A control circuit 306 is coupled between tracking circuit 302 and I/O circuit 112 for receiving the delayed control signal CTRL and generating a clock signal for I/O circuit 112. An example of control circuit 306 is an inverter that simply inverts the delayed control signal CTRL. FIG. 3A shows that dummy bit line DBL is coupled to power supply voltage Vcc through a precharging PMOS transistor 308.
FIG. 3B shows the detailed structure of one tracking cell 304, which includes 6 transistors, i.e., PMOS transistors 310 and 312 and NMOS transistors 314, 316, 318, and 320. As shown in FIGS. 2 and 3B, tracking cell 304 has a structure similar to memory cell 104, except that the gates of PMOS transistor 310 and NMOS transistor 314 are coupled to power supply voltage Vcc, and that the gate of NMOS transistor 318 is coupled to control signal CTRL. Also as shown in FIG. 3B, dummy bit line DBL_ is floating and not used, while dummy bit line DBL is coupled to I/O circuit 112 through control circuit 306 for generating the clock signal for I/O circuit 112.
When memory array 102 is not accessed, control signal CTRL is at logic 0, and dummy bit line DBL is pre-charged to a voltage level approximately equal to Vcc. When a memory cell 104 of memory array 102 is being accessed, control signal CTRL changes to logic high, turning off PMOS transistor 308 and turning on NMOS transistor 318. At the same time, word line signal WL is at logic high, and NMOS transistor 320 is turned on. Because NMOS transistor 314 is always turned on, precharged dummy bit line DBL is discharged through NMOS transistors 318 and 314. When the voltage on dummy bit line DBL drops below a flipping point, control circuit 306 generates a clock signal and I/O circuit 112 is triggered. Therefore, I/O circuit 112 is now triggered not by control signal CTRL, but rather is triggered by the clock signal generated by control circuit 306, which represents control signal CTRL delayed by the process of discharging dummy bit line DBL. Because tracking cell 304 has a structure similar to memory cell 104, the process of discharging dummy bit line DBL closely resembles the discharging process of bit lines BL or BL_ of memory cells 104. At the same time, control signal CTRL or a signal synchronized to control signal CTRL is used, without delay, to select and activate one of memory cells 104. Thus, through careful design of tracking cells 304, e.g., through control of the size of the six transistors of each tracking cell 304, the time period for discharging precharged dummy bit line DBL may be controlled to correspond to the time required to discharge the bit line BL or BL_ associated with the selected memory cell 104, such that a desirable read margin is achieved.
Memory devices are generally designed to operate at a certain power supply voltage, such as 1.2 V. But often the memory devices also need to operate at lower power supply voltages, such as 0.9 V or even lower. A problem with memory device 100 of FIG. 3A is that, when power supply voltage Vcc is lowered, the read margin decreases accordingly, because the time period required to discharge precharged dummy bit line DBL is approximately proportional to how much charge is stored thereon, which is in turn approximately proportional to Vcc. For example, with the conventional tracking circuit shown in FIG. 3B, memory device 100 may have a read margin of above 100 mV when Vcc is 1.2 V or above, but may have a read margin of less than 60 mV when Vcc is 0.8 V. If I/O circuit 112 is capable of detecting only a differential voltage of 100 mV or above, a read margin of 60 mV will result in read failures. Thus, a minimum operable power supply voltage, VCCMIN, is largely limited by the tracking circuit. On the other hand, if Vcc is high, the process of discharging dummy bit line DBL takes longer time, and the read margin of memory device 100 may be significantly higher than 100 mV, resulting in unnecessary power consumption.